Challenges in Device Development
As semiconductor device manufacturers and designers move from planar devices to structures built with complex 3D shapes, with air gaps, or with novel materials the complexity of manufacturing and gate level failure analysis increases dramatically. Identifying defects or resolving material interfaces in a FIB cut cross-section requires highly precise endpointing, surface preparation, and SEM imaging performance. For atomic level defects or compositional analysis, creating ultra-thin lamella for transmission electron (TEM) or atom probe (APM) microscopy that capture the correct region of interest (ROI) presents other challenges. Due to limited floorspace and budgets, labs are continually pushing to have best in class performance for each of these sample workflows in one sample preparation system.
- Ultra thin (<10nm) samples
- New materials
- Complex deposition techniques
- New analytical techniques (eg. atom probe)
- Atomic level engineering
- High resolution strain measurement
Meet our newest innovative products
Our latest next-generation products focus on advanced analytical capabilities for failure analysis and process control. These solutions are designed to help increase productivity in semiconductor fabs and labs by improving quality control and yield in the manufacture of 3D NAND, logic, DRAM, analog and display devices.